(A) Field of the Invention
The present invention relates to a memory cell structure and method for fabricating the same, and more particularly, to memory cell structure having a transistor with source and drain positioned on a semiconductor substrate and the method for fabricating the same.
(B) Description of the Related Art
FIG. 1 illustrates a semiconductor transistor structure according to a prior art. The semiconductor transistor structure comprises a gate structure positioned on a semiconductor substrate 100, which has an isolation device 102 to isolate the transistors on the semiconductor substrate 100. The gate structure comprises a gate oxide layer 104 positioned on the semiconductor substrate 104, a polysilicon gate 106 positioned on the gate oxide layer 104, and a nitride layer 108 positioned on the polysilicon gate 106. Spacers 112 are positioned on the sidewalls of the gate structure. Lightly doped drain (LDD) regions 110 are positioned in the semiconductor substrate 100, and a source/drain 114 is positioned in the semiconductor substrate 100 and nearby in the LDD regions 110. In addition, the semiconductor transistor structure further comprises an oxide layer 116 positioned on the semiconductor substrate 100, and contacts 118 in the oxide layer 116.
As semiconductor transistor structures become smaller, the conventional dynamic random access memory structure can no longer meet the requirements of junction leakage current and subthreshold leakage current. Although the subthreshold leakage current can be reduced by increasing the channel doping concentration up to 4×1018 cm−3, the junction leakage current will increase dramatically as a result of tunneling current between band to band.